This invention relates to a control system for a frame memory that temporarily stores data to be displayed on a raster display device.
Computing systems such as personal computers and work stations commonly employ a raster display device such as a cathode-ray tube which is scanned in a series of horizontal raster lines. Image data are written by the computing system in a frame memory, from which they can repeatedly be read out and sent to the raster display device, thereby refreshing the image on the display screen. When standard, single-port memory elements are used, write access cycles are interspersed as necessary between display access cycles, or executed during retrace blanking periods of the raster display.
Recently high-resolution raster devices displaying up to 2000 dots in both the horizontal and vertical directions have come into use. The rate at which these displays must be kept refreshed with display data strains the capabilities of single-port memory elements and leaves little time for write access. The frame memories of such systems therefore employ dual-port memory elements having a parallel port for write access and a serial port for display access.
Besides supplying output data at the rates required by by high-resolution raster displays, these dual-port memories alleviate restrictions on write access timing, since write access via the parallel port can take place at the same time as output via the serial port. These dual-part memories necessitate complex control systems, however, because write access and display access take place at different speeds, and the write access addresses and the display access addresses must be generated separately. A particular control problem arises because the raster display device may employ either sequential scanning, in which the rasters are scanned in sequence from the top to the bottom of the screen, or interlaced scanning, in which first the even-numbered rasters are scanned, and then the odd-numbered rasters are scanned.
Prior-art control systems, consisting of a write address generator, a display address generator, and a selector for selecting either the write address or the display address, are built for use with a particular type of display: either sequential or interlaced. Thus they lack general applicability. In the case of interlaced scanning, some prior-art control systems also lack means for efficient memory utilization.